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Computer architecture

Paper 1

This section is examined in Paper 1.

The Central Processing Unit (CPU) and Microprocessors
Learning Objective 1 & 2: The Central Processing Unit (CPU) is the component responsible for processing instructions and data. Its primary role is to manage the flow of data through the computer and execute the fetch–decode–execute (FDE) cycle.

A microprocessor is a specific type of CPU where all the essential components (Control Unit, ALU, registers, etc.) are integrated onto a single silicon chip. This integration allows for high speed and compact size.

Learning Objective 3: In a Von Neumann architecture, the CPU shares a single bus for both data and instructions. This creates a bottleneck because the CPU cannot fetch an instruction and read/write data at the exact same time from memory. To manage this, the CPU uses specific registers to hold addresses and data temporarily while they are being transferred.
CPU Components in Von Neumann Architecture
To understand the CPU, we must define its internal components. These work together to execute programs.
Description
Manages the flow of data and instructions. It decodes instructions and sends control signals to other components.
Carries out all arithmetic (e.g., addition) and logic (e.g., comparison) operations.
A register that stores the result of calculations performed by the ALU. It does not store the calculation itself, but the final outcome.
Stores the instruction currently being decoded or executed. It is built into the Control Unit.
Holds the address of the memory location that is to be accessed (read from or written to).
Holds the data that has been fetched from memory or is about to be sent to memory.
Stores the address of the next instruction to be fetched. It is incremented after each fetch.
The Fetch–Decode–Execute (FDE) Cycle
Learning Objective 4: The FDE cycle is the process by which the CPU retrieves and processes instructions. Below is the detailed sequence for the Fetch stage, followed by Decode and Execute.
Process
  1. The address of the next instruction is copied from the Program Counter (PC) to the Memory Address Register (MAR) via the address bus.
  2. The PC is incremented by 1 (or the size of the instruction) so it points to the subsequent instruction.
  3. The instruction at that address in RAM is fetched and copied to the Memory Data Register (MDR) via the data bus.
  4. The instruction is then copied from the MDR to the Current Instruction Register (CIR).
The Control Unit (CU) decodes the instruction in the CIR. It separates the instruction into an opcode (what to do) and an operand (where the data is).
The decoded instruction is executed. For example, if it is an arithmetic operation, the ALU performs the calculation, and the result is stored in the Accumulator.
⚠︎ Register and Component Errors
Mistake 1: Identifying the CIR as part of the ALU.
Correction: The CIR is built into the Control Unit (CU), not the ALU. The CU decodes the instruction; the ALU executes arithmetic operations.
Mistake 2: Saying the Accumulator stores 'calculations'.
Correction: The Accumulator stores the result of a calculation. It holds the final value after the ALU has processed the data.
Mistake 3: Confusing MDR and MAR roles in Fetch.
Correction: The address goes to the MAR. The data/instruction comes from RAM into the MDR. Do not send the address to the MDR.
Describing the Fetch Stage Accurately
Context: When asked to describe the fetch stage, examiners look for specific register names and bus usage.

Why this is accepted: Vague descriptions like 'the CPU gets data' are rejected. You must specify which registers move what data via which bus.

Correct Phrasing: 'The address from the PC is sent to the MAR via the address bus. The instruction at that address is fetched into the MDR via the data bus, then copied to the CIR.'

Note on Pipelining: While modern CPUs use pipelining (overlapping stages), for exam purposes, describe the logical sequence of one complete fetch cycle as above.

CPU Performance Factors: Cores, Cache, and Clock Speed
Learning Objective 5: Three key factors affect CPU performance.
Explanation and Impact on Performance
Measured in Hertz (Hz). It determines the frequency at which the CPU can perform operations within each stage of the FDE cycle. Higher clock speeds allow stages to complete faster, increasing the overall rate of instruction processing.

Note: In pipelined processors, higher clock speed means each stage advances more quickly, allowing more instructions to be processed per second.

A core is an independent processing unit within the CPU. Multiple cores allow for true parallel processing of different instructions or threads.

Impact: This significantly improves performance in multitasking and multi-threaded applications, as different cores can work on different tasks simultaneously, unlike a single-core CPU which relies on rapid switching (time-slicing).

Cache is a small amount of very fast Static RAM (SRAM) located directly on the CPU die. It stores frequently used data and instructions.

Levels: L1 cache is fastest/smallest/closest to the core; L2/L3 are larger but slightly slower.

Impact: Without cache, the CPU would spend most of its time waiting for data from the much slower main RAM (DRAM). Larger cache reduces 'cache misses' and latency.

⚠︎ Performance Misconceptions
Mistake 1: Saying cache stores data 'just used' or 'about to be used'.
Correction: Cache stores frequently used data and instructions. It is a subset of memory that the CPU accesses most often.
Mistake 2: Saying clock speed means 'more FDE cycles are carried out simultaneously'.
Correction: Clock speed determines how fast each stage completes. Multi-core processors allow simultaneous execution. Do not confuse speed (time) with cores (parallelism).
Explaining Clock Speed and Cores
Context: When explaining how clock speed affects performance.

Why this is accepted: Examiners want to see the link between frequency and instruction processing rate.

Correct Phrasing: 'A higher clock speed means the CPU can perform more operations per second. This allows the FDE cycle stages to complete faster, increasing the number of instructions processed in a given time.'

For Cores: 'More cores allow the CPU to execute multiple instructions simultaneously (parallel processing), improving performance for multitasking.'

Instruction Sets and Embedded Systems
Learning Objective 6: An instruction set is the complete list of basic operations (instructions) that a CPU can perform. It defines the machine language the CPU understands.

Key Point: Different CPUs have different instruction sets (e.g., x86 vs ARM). Software must be compiled into the specific instruction set of the target CPU.

Learning Objective 7: An embedded system is a computer system designed to perform a dedicated, single function within a larger system.

Characteristics:

  1. Dedicated Function: It does one specific task (e.g., washing machine control).
  2. Dedicated Hardware: The hardware is tailored for that specific function.
  3. Limited Resources: Often has limited memory and processing power compared to general-purpose computers.
  4. Real-time Operation: Must respond to inputs within strict time constraints.
⚠︎ Embedded System vs. General Computer
Mistake: Saying an embedded system is 'small' or 'cheap'.
Correction: Size and cost are not defining features. A supercomputer is large but not embedded. A smartwatch is small and embedded.

Correct Distinction: An embedded system has a dedicated/single function and dedicated hardware. A general-purpose computer can perform many different functions using the same hardware.

Identifying Embedded Systems
Context: When asked to explain why a device is (or is not) an embedded system.

Why this is accepted: Examiners look for the concept of 'dedication' vs 'generality'.

Correct Phrasing: 'A calculator is an embedded system because it is designed to perform a single, dedicated function (calculations) using dedicated hardware. A laptop is not embedded because it can run many different applications.'

Practice Questions
Q:
Explain why a digital calculator is considered an embedded system rather than a general-purpose computer. [2]
A:
  1. It performs a dedicated/single function (calculations).
  2. It has dedicated hardware designed specifically for that function.
Q:
Describe the role of the Program Counter (PC) in the fetch stage of the FDE cycle. [2]
A:
  1. It stores the address of the next instruction to be fetched.
  2. It is incremented after the address is sent to the MAR.
Q:
Explain how increasing the clock speed of a CPU affects its performance. [3]
A:
  1. Clock speed determines the frequency of operations/stages in the FDE cycle.
  2. Higher speed means stages complete faster.
  3. This allows more instructions to be processed per second.
Q:
State the purpose of the Accumulator register. [1]
A:
It stores the result of calculations performed by the ALU.
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